1. Field of the Invention
This invention relates generally to the structure and fabrication process for packaging the integrated circuit (IC) devices formed on a semiconductor substrate. More particularly, this invention relates to a novel fabrication process where chip scale connection and packaging processes in a conventional method are now replaced by wafer scale packaging processes. Simplified production techniques with time and cost savings are achieved.
2. Description of the Prior Art
Conventional processes for producing the integrated circuit (IC) packages are often performed after the die separation even though time and cost savings can be achieved by carrying out wafer scale packaging process before the die separation. This is due to the concerns that when a wafer is mounted on a board, a thermal cycle may cause damages to the wafer. This difficulty is caused by the different coefficients of the thermal expansion between the wafer and the board upon which the IC chip is mounted. The stress caused by the difference in thermal expansion can break a wafer. Due to this difficulty, the benefits of carrying out a wafer-scale packaging process to achieve time and costs saving s cannot be realized. Instead, in a conventional process, the wafers are first divided into hundreds or thousands of dies, and the packaging processes are performed on each individual chip. Additional efforts are required to handle so many individual chips and duplicated processing steps that take more times and labors are necessary to carry out the packaging processes on each chip. Conventional packaging technology does not offer an effective solution to circumvent the concerns that a delicate wafer may be damaged when mounted on a carrier for further packaging processes when there are differences in thermal expansion coefficients.
Therefore, a need still exits in the art of integrated circuit (IC) package to provide a novel structural configuration and fabrication process that would resolve these difficulties. More specifically, it is preferably that a wafer scale packaging process can be conveniently performed without requiring additional complicated processing steps. It is further desirable to employ regular manufacture process commonly applied to reduce the production costs such that IC packages of high quality with high performance can be economically produced.
It is therefore an object of the present invention to provide a new wafer level packaging method and configuration wherein stress imposed on the wafer caused by differences of thermal expansion is minimized such that aforementioned limitations and difficulties as encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a new wafer level packaging method and configuration. The wafer is first mounted on a mounting and packaging carrier. The stress imposed on the wafer caused by differences of thermal expansion between the wafer and the mounting carrier is minimized by providing chipisolation and stress relief configuration either on the wafer or on the chip-mounting carrier. The stress induced from differences in thermal expansion when carrying out the wafer-level packaging processes is relieved without transferring to the wafer.
Another object of the present invention is to provide a new wafer level packaging method and configuration. The wafer is first mounted on a mounting and packaging carrier. The wafer is then divided into individual chips by sawing the wafer along the predefined scribe lines and filled with flexible gap-filling and insulation materials. The stress imposed on the wafer caused by differences of thermal expansion between the wafer and the mounting carrier is minimized by providing chip-isolation and stress relief configuration with gaps between the chips filled with flexible gap-filling materials. The stress induced from differences in thermal expansion when carrying out the wafer-level packaging processes is relieved without transferring to the wafer.
Another object of the present invention is to provide a new wafer level packaging method and configuration. The wafer is first mounted on a mounting and packaging carrier, e.g., a rigid interposer. The rigid interposer is provided with chip stress-relief and isolation means having open trenches along the edges of areas under each individual chip. The stress imposed on the wafer caused by differences of thermal expansion between the wafer and the mounting carrier is isolated and relieved with the open trenches allow flexibility of expansions. Under-fill materials provided between the wafer and the rigid interposer also absorbs the stress. The stress induced from differences in thermal expansion when carrying out the wafer-level packaging processes is relieved without transferring to the wafer.
Briefly, in a preferred embodiment the present invention discloses a wafer level packaging method and configuration. This improved wafer level package includes a processed wafer mounted on a first printed circuit board (PCB) carrier. The processed wafer mounted on the PCB carrier board includes a plurality of separated integrated circuit (IC) chips divided by scribe-line gaps wherein each of these scribe-line gaps is filled with flexible gap-filling insulation material. In another preferred embodiment, the wafer-level package further includes a second PCB carried board composed of same material as the first PCB carrier board mounted on top of the wafer. In another preferred embodiment, the wafer-level package, which having the first and the second PCB carrier boards further includes a plurality of connection via penetrating through the first and the second PCB carried board for forming electric connection to the IC chips separated by the scribe-line gaps.
The present invention further discloses a method for carrying out a wafer-level packaging manufacturing process. The method includes the steps of (a) mounting a processed wafer onto a first printed circuit board (PCB) carrier; (b) dividing the processed wafer into a plurality of integrated circuit (IC) chips by opening a plurality of scribe-line gaps between each of the IC chips; (c) filling each of the scribe-line gaps with flexible gap-filling insulation material; (d) mounting a top PCB carrier board on top of the processed wafer composed of identical material as that of the first PCB carrier board; and (d) forming a plurality of via-connections by opening a plurality of vias penetrating the first and the second PCB carrier boards and filling the vias with conductive material for electrically connecting to the separated IC chips.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.